This application claims priority to Korean Patent Application No. 2003-54349, filed on Aug. 6, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a phase mixer and a control method thereof.
2. Description of the Related Art
As electronic devices operate at higher speeds, faster central processing units (CPUs), faster memory devices, and faster peripheral devices are needed. Phase locked loop (PLL) circuits or delay locked loop (DLL) circuits are commonly used in semiconductor integrated to generate an internal clock signal in synchronization with an external clock signal.
The PLL or DLL circuit measures a phase difference between the internal clock signal generated by the PLL or DLL circuit and the external clock signal and shifts the phase of the internal clock signal so as to reduce the phase difference. When shifting the phase of the internal clock signal, several reference signals are generated . The two reference signals that most closely coincide with the external clock signal are selected, and an internal clock signal having the same phase as the external clock signal is generated by interpolating the selected reference signals.
During interpolation, a weighted average of the selected reference signals is calculated by weighing each of the selected reference signals by a predetermined percentage in a phase mixer of the PLL circuit or the DLL circuit. The phase mixer is also called a phase blender. A conventional phase mixer is disclosed in U.S. patent application Ser. No. 2002/0140491.
A high quality PLL circuit or DLL circuit has a wide frequency range and can track an external clock signal despite process, voltage, and temperature (PVT) variations. However, when a phase mixer performs interpolation, a shouldering effect (described later) is generated due to frequency variation and PVT variation, and jitter can be generated. To prevent this phenomenon, slew rates of signals input to the phase mixer, that is, the selected reference signals, must be controlled according to frequency variation and PVT variation of the selected reference signals.
FIG. 1 is a graph illustrating a first method by which a conventional phase mixer generates a third signal 103 by interpolating first and second signals 101 and 102 having different phases. FIG. 2 is a graph illustrating a second method by which a conventional phase mixer generates a third signal 203 by interpolating first and second signals 201 and 202 having different phases. In FIGS. 1 and 2, the third signals 103 and 203 are obtained by averaging the first signals 101 and 201 and the second signals 102 and 202 after weighing each of the first signals 101 and 201 and the second signals 102 and 202 by 0.5.
With reference to FIG. 1, when the rise time and the fall time of the first signal 101 and the second signal 102 occupy a relatively large percentage of the respective periods of the first and second signals 101 and 102, frequencies of the first and second signals 101 and 102 are high, and PVT variations are high. An interpolated output signal, that is, the third signal 103, is a signal averaging the first signal 101 and the second signal 102. PVT variations can occur due to a number of factors including bad transistor characteristics, a minimal power source, and high ambient temperature.
With reference to FIG. 2, when the rise time and the fall time of the first signal 201 and the second signal 202 occupy a relatively small percentage of the respective periods of the first and second signals 201 and 202, frequencies of the first and second signals 201 and 202 are low, and the PVT variations are low. During a period when the first signal 201 is at a logic high and the second signal 202 is at a logic low, distortion exists in the interpolated output signal, that is, the third signal 203. This phenomenon is known as the shouldering effect. The PVT variations are small because process parameters make good transistor characteristics, a maximal power source, and low ambient temperature.
Therefore, conventionally, to prevent an interpolation output signal from being distorted, slew rates of input signals of a phase mixer are controlled by connecting a capacitor with a predetermined capacity to an input terminal of the phase mixer for a specific frequency or under a specific PVT condition. However, while such method may be effective for a specific case, it may not work well for a broader range of frequencies or other PVT conditions.
A need therefore exists for a phase mixer that is insensitive to frequency variations and PVT variations, and capable of automatically controlling slew rates of input signals in view of frequency variations and PVT variations.